A designer conventionally generates a model of a hardware system. This model may be in the form of a block diagram. This block diagram may have many modules, where one module communicates with another module through data. For example, a first module may receive data, process such data, and send such processed data to another module. Accordingly, within such a model there may be many modules, many blocks within modules, and these blocks may include internal data interfaces for communicating or moving data from one module to another. These internal interfaces may be distinguished from external interfaces, such as for example standardized interfaces for which raw data may be input to and processed data may be output from such model. For example, a model of a hardware system may be written for prototyping for example in a High-Level Modeling System (“HLMS”) or High-Level Synthesis (“HLS”) tool for subsequent synthesis to a production design. A designer working with an HLMS or HLS tool, or directly writing a code for such a model in a Hardware Description Language (“HDL”) (e.g., VHDL or Verilog), a Register Transfer Language (“RTL”), or C-to-gates code (e.g., C-to-HDL or C-to-RTL), heretofore would construct these internal data interfaces between modules, which was a time consuming process.
Accordingly, it would be desirable and useful to further automate design of a hardware system by reducing the amount of effort in generating internal data interfaces therefor.